1. Field of the Invention
The present invention relates to a shift register, and more particularly, to a shift register capable of suppressing a transient spike.
2. Description of Prior Art
With a rapid development of monitor types, novel and colorful monitors with high resolution, e.g., liquid crystal displays (LCDs), are indispensable components used in various electronic products such as monitors for notebook computers, personal digital assistants (PDAs), digital cameras, and projectors. The demand for the novelty and colorful monitors has increased tremendously.
Referring to FIG. 1 showing a block diagram of a conventional LCD device 10, the LCD device 10 includes a LCD panel 12, a gate driver 14, and a source driver 16. The liquid crystal panel 12 includes a plurality of pixels, each pixel having three pixel units 20 indicating three primary colors, red, green, and blue. For example, the liquid crystal display 12 with 1024 by 768 pixels contains 1024×768×3 pixel units 20. The gate driver 14 periodically outputs a scanning signal to turn on each transistor 22 of the pixel units 20 row by row, meanwhile, each pixel units 20 is charged to a corresponding voltage level based on a data signal from the source driver 16, to show various gray levels. After a row of pixel units is finished to be charged, the gate driver 14 stops outputting the scanning signal to this row, and then outputs the scanning signal to turn on the transistors 22 of the pixel units of the next row sequentially until all pixel units 20 of the liquid crystal panel 12 finish charging, and the gate driver 14 outputs the scanning signal to the first row again and repeats the above-mentioned mechanism.
In conventional liquid crystal displays, the gate driver 14 functions as a shift register. In other words, the gate driver 14 outputs a scanning signal to the liquid crystal panel 12 at a fixed interval. For instance, a liquid crystal panel 12 with 1024×768 pixels and its operating frequency with 60 Hz is provided, the display interval of each frame is about 16.67 ms (i.e., 1/60 second), such that an interval between two scanning signals applied on two row adjacent lines is about 21.7 μs (i.e., 16.67 ms/768). The pixel units 20 are charged and discharged by data voltage from the source driver 16 to show corresponding gray levels in the time period of 21.7 μs accordingly.
Referring to FIG. 2 illustrating accumulated transient spike via multiple stages of the shift register, each stage of the shift register which is for use in the gate driver 14 manufactured by using Low Temperature Poly-Silicon (LTPS) processes may export a transient spike 40 which is induced by a spike 40 from previous two stage. Therefore, the unwanted spike accumulates and increments stage by stage. In case of a magnitude of the accumulated spike in excess of the output pulse 42, pixel units start charging even if the output pulse 42 does not received. In this way, the pixel units to be charged upon a reception of the transient spike 40 results in an incorrect display view.